1. Field of the Invention
The present invention relates to a capacitor sheet, and in particular to a capacitor sheet for removing noises of an LSI or the like on a circuit substrate in a general electronic apparatus such as a communication apparatus or equipment.
2. Description of the Related Art
In order to suppress noises emitted from a circuit substrate and to stabilize a signal waveform, an electronic part such as an IC or an LSI mounted on the circuit substrate mounts a capacitor in the vicinity between a power supply pin and a ground of the IC, the LSI, or the like, for the power supply.
FIGS. 12A-12C show such prior art capacitor mounting technologies.
Firstly in the prior art example shown in FIG. 12A, in order to realize a high-density mounting, an electronic part such as the IC or the LSI uses a ball grid array (hereinafter, abbreviated as BGA) 21 for the circuit substrate. On the BGA 21, a grounding bump (electrode) 211 and a signal/power supply bump 212 are provided downwardly. Through these bumps 211, 212 and a pattern wiring 23 similarly provided upwardly on a printed wiring board 22 as the circuit substrate, signals and power are supplied to the printed wiring board 22.
In order to remove noises from the electronic part, a through-hole (via-hole) electrode 24 is provided within the printed wiring board 22, to which a noise removing capacitor 26 is connected through a pattern wiring 25 provided on the opposite side of the printed wiring board 22 as seen from the BGA 21.
FIG. 12B shows an arrangement in case where the location of the grounding bump 211 and the signal/power supply bump 212 is displaced toward the right side.
Also, in FIG. 12C, BGA's 21_1 and 21_2 are provided on both sides of the printed wiring board 22. In this case, an internal layer solid (SG) 27 is provided within the printed wiring board 22. By this internal layer solid 27, a plurality of through-hole electrodes 24 provided within the printed wiring board 22 are mutually connected. In the example of FIG. 12C, the through-hole electrodes 24 provided on the right and the left ends of the printed wiring board 22 and the capacitors 26 are connected through the pattern wirings 23 and 25 provided between the signal/power supply bumps 212.
However, the pattern wirings 23 and 25 for power supply exist between the BGA's 21 (21_1 and 21_2) and the capacitor 26 in all of the prior art examples shown in FIGS. 12A-12C. Therefore, when the BGA 21 mounts thereon a high-frequency circuit with a short wavelength, such pattern wirings 23 and 25 can not be neglected, and an inductance component by the pattern wirings prevents an effective suppression of a switching noise in a power supply path, which has been a factor of an unstable operation.
As a method of removing the inductance component by the pattern wirings, a conventional technology of sandwiching a capacitor 28 made of high dielectric constant material between the BGA 21 and the printed wiring board 22, as shown in FIG. 13, has also been proposed. It is to be noted that the BGA 21 is connected to the capacitor sheet 28 through the grounding bump (BGA electrode) 211 and the signal/power supply bump 212, and the capacitor sheet 28 is connected to the printed wiring board 22 through a grounding footprint 221 and a signal/power supply footprint 222.
As another conventional technology, there are a bypass capacitor and a formation method thereof wherein a BGA package is mounted on a printed board with a high dielectric constant material sheet sandwiched therebetween, a high dielectric constant material is .almost as large as the area in which power supply electrodes and grounding electrodes, within board attaching electrodes provided on the rear surface of a BGA base board of the BGA package are formed, and apertures are formed at parts corresponding to the power supply electrodes and the grounding electrodes so that electrical connection to a BGA mounting pad of the printed board is not blocked (see e.g. patent document 1).
As further conventional technology, there are an integrated circuit device and a capacitor for an integrated circuit wherein :a capacitor is mounted between an integrated circuit chip and a wiring board in an integrated circuit device in which the integrated circuit chip is flip-chip-mounted on the wiring board, the capacitor has a pair of first electrode pads connected to one electrode of the capacitor, and a pair of second electrode pads connected to the other electrode, one of the first electrode pads is connected to a power supply electrode of the integrated circuit chip, the other of the first electrode pads is connected to the power supply terminal of the wiring board respectively, one of the second electrode pads is connected to a grounding terminal of the integrated circuit chip, and the other of the second electrode pads is connected to the grounding terminal of the wiring board respectively (see e.g. patent document 2).
[Patent document 1] Japanese patent application laid-open No.9-102432
[Patent document 2] Japanese patent application laid-open No.2003-124430
In the above-mentioned patent document 1, there is a problem that a power supply point associated with the BGA package is determined, and an electrode location providing a capacitance is fixed.
Also, in the above-mentioned patent document 2, the power supply terminals and the grounding terminals of an IC or an LSI have to be arranged at adjoining or vicinal positions in order to form the capacitor between the first electrode and the second electrode, and there is a possibility that no capacitor can be formed depending on a pin arrangement of the IC or the LSI.
Namely, since a method of providing the capacitance sideward by assigning the power supply and the ground to adjoining two pins in such a conventional capacitor forming technology, only one kind of capacitor lamination is formed, and a capacitor function is performed only in the case of a single power supply of the BGA. Accordingly, in order to accommodate to the case where a plurality of power supplies exist (when e.g. 3.3 V, 1.8 V, and the like are used) in the BGA, a plurality of dielectric layers and a plurality of power supply layers sandwiching the dielectric layers have to be formed, and custom products have to be provided according to kinds of power supplies, which leads to a problem of lacking in flexibility.